In memories, operations such as read and/or write take place in response to an enable signal, for example, a write enable signal. The write enable signal may be driven by a system clock, with an operation taking place at an operable clock edge of the system clock. Memories may require timing for further operations associated with the read and/or write operations. For example, timing for control operations of the memory, such as a bit line precharge, a word line assertion, and/or a sense amplifier enable, etc.
Self-timed memories may provide these control timings independently of the system clock. These self-time memories may include additional circuitry for the generation of self-time control signals. However, operating conditions of a memory may affect the timing required for the memory. For example, memory components may require more time to operate correctly under low power conditions. Additionally, different requirements for the memory performance, for example, a high speed or low power performance, may affect the timing of the self-timed operations.
Some memories may have built-in-self-test BIST capabilities in order to test the functioning of the memory. Other memories may have a test mode of operation in order to test the functionality of the memories. The testing of the memory may involve the external monitoring of data written to and read from the memory, and typical may take a number of clock cycles to identify an error.